中原大學九十三學年度碩士班入學招生考試
93年3月27日　11:00~12:30　電子系數位與類比系統組　 誠實是我們珍視的美德，
我們喜愛「拒絕作弊，堅守正直」的你！
科目：數位電路  
1. Convert the decimal number 98.3125 to hexadecimal and then from hexadecimal convert it to binary. (5%)
     
2. (a). Perform the following operations using signed-2's complement representation and enough digits to accommodate the numbers.
    (1). 7 + 23 (5%) (2). 7 - 23 (5%)
  (b). Design a "binary adder-subtractor" that can implement the above operations using the same circuit. The definition of all input/output pins is shown in Fig. P2. (** You can use Full-Adder as the basic building block.) (10%)
   
     
3. (a). Simplify the following expression in (1) Sum of Products (5%) (2) Product of Sums. (5%)
F(w, x, y, z) = Σm(2, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15)
  (b). Implement the above Sum of Products expression with two-level NAND gate circuits. (5%)
  (c). Implement the above Product of Sums expression with two-level NOR gate circuits. (5%)
  (d). Implement the above Boolean expression with a 8-to-1 line Multiplexer and external gates, if needed. (5%)
     
4. (a). Is the circuit shown as Fig. P4-1. a Mealy machine or Moore machine? (5%)
  (b). Construct a state table and state graph for the circuit shown as Fig. P4-1. (20%)
  (c). Complete the timing diagram shown as Fig. P4-2, the delays of flip-flops have to be included. (10%)
   
   
     
5. Reduce the following state table to a minimum number of states. (15%)
   
 
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