| 所組別: | 電子工程學系乙組 | 科目: | 數位電路 | 考試時間: | 4月29日第2節 |
| (a)Plot the following function on a Karnaugh map. (10%) |
| F(A, B, C, D) = A’B’ + CD’ + ABC + A’B’CD’ + ABC’D |
| (b)Find the minimum sum of products. (10%) |
| (c)Find the minimum product of sums. (10%) |
| Find a minimum network of 2-input AND and 2-input OR-gates to realize |
| F(A, B, C, D) = Σm(0, 1, 2, 3, 4, 5, 7, 9, 11, 13, 14, 15) |
| Determine the output waveform X for the circuit shown in Fig. 1, directly from the output expression. |
| Realize a clocked J-K flip-flop by using a clocked D flip-flop and other external gates. |
| Complete the timing diagram for the following circuit. Note that the CK inputs on the two flip-flops are different. |
| Given the logic package A shown in Fig. 2, which operates as follows: output yi = 1 iff (if and only if) i inputs out of x0, x1, x2 are equal to 1. Design unit B so that the overall logic function of unit C will be to produce an output zi = 1 iff i inputs out of x0, x1, x2, x3 are equal to 1. (i.e., to find zi = f(x3, y0, y1, y2, y3) where xi can be xi or xi’) |