| 所組別 : | 電子工程學系乙組 | 科目 : | 數位電路 | 考試時間 : | 05月01日第2節 |
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(1)(5%) Please give a typical timing diagram for the system.

(2)(5%) Let us include only one D flip-lop in the circuit, and label this flip-flop Y. Please give the next-value table Y v+1for the system.

(3)(5%) Please obtain a minimal sum-of-products input logic for the D flip-flop from the above table.
(4)(5%) Please give a tabulation of output values as a function of the input and flip-flop values.

(5)(5%) Please obtain a minimal sum-of-products expression for the output z from the above table.
(6)(5%) Please give a circuit realization for the system.


The AM section of the instruction (bits 5-7) specifies the addressing mode, which determines how the 8 address bits (8-15) are used. There are five addressing modes for the computer as shown below.

We will investigate the effect of the different addressing mode on the instruction shown in the following memory.

The instruction in addresses 250 and 251 is "move to AC" with the address field equal to 500. The program counter PC has the number 250 for fetching this instruction. The accumulator register AC will receive the operand after the instruction is executed. The opcode assigned to MOVE is (00101)2. Assume the index register IX has a value of 100 now.
In the following table, please list the decimal value of the effective address and the operand to be loaded into the AC for different binary instructions in address 250.
| Instruction | Effective Address | Operand |
| (00101000)2 | ||
| (00101001)2 | ||
| (00101010)2 | ||
| (00101011)2 | ||
| (00101100)2 |
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