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中原大學九十三學年度碩士班入學招生考試
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| 93年3月27日 16:00~17:30 資訊工程學系 | 誠實是我們珍視的美德, 我們喜愛「拒絕作弊,堅守正直」的你! |
| 科目:計算機系統 |
| 1. | (15%,每小題3分) What are the differences between the following pairs? | |
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1)
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Logical address space, Physical address space. | |
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2)
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Paging, Segmentation. | |
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3)
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Deadlock prevention, Deadlock avoidance. | |
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4)
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Kernel-level threads, User-level threads. | |
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5)
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A trap, An interrupt. | |
| 2. | (10%) | |
| (3分) | 1) What is a race condition? | |
| (3分) | 2) Give an example of a race condition. | |
| (4分) | 3) Use either the semaphore or the monitor and explain how it can be used to prevent race conditions. | |
| 3. | (15%) | |
| (4分) | 1) Under what situations of a process, CPU scheduling decisions may take place? | |
| (4分) | 2) What is meant by preemptive and non-preemptive scheduling? | |
| (3分) | 3) Among these situations in 1) above, which are preemptive? | |
| (4分) | 4) What are optimization criteria for CPU scheduling? | |
| 4. | (10%) | |
| (6分) | 1)What are the major file operations in file management? | |
| (4分) | 2)Explain why the file operations used in many modern systems to interact with devices as well? | |
| 5. | (20%,每小題10分) | |
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1)
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Assuming a 2-way set-associative cache with 16-word data capacity and 2-word blocks, and the size of the main memory is 4 KB, determine the lengths of the physical address, the tag, the index, the block offset and the block offset fields. Use a diagram to show the layout of an implementation of the cache including the hit/miss detection mechanism. | |
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2)
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The cache is initially empty. The replacement policy is first-in-first-out.
A series of address references given as word addresses is
as follows : 8 , 10 , 9 , 16 , 1 , 13 , 9 , 7 , 6 , 16 Label each reference in the list with its index, and mark whether it is a hit or a miss. Show the final content of the cache. |
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| 6. | (15%) | |
| To improve the performance of a pipelined processor, a forwarding circuit is usually adopted to resolve most of the data hazard. Considering the following 7-stage pipeline for a load/store machine, describe a forwarding circuit most appropriate to the processor. In your description, indicate what information should be used in making the forwarding decision, and from which pipeline latches these information are to be collected. | ||
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| 7. | (15%) | |
Given a computation algorithm as follows, express the algorithm
using algorithmic-state-machine (ASM) chart, design a datapath for the algorithm
with control input(s) and status signal(s) identified, and devise the state
transition diagram for the corresponding control unit. Design a corresponding
control unit. |
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~ End ~
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