- Suppose program 1 runs in t1= 4.0s on machine A and program 2 runs in t2=1.2s on machine A. What mean should be used to combine t1 and t2 (give the name and write the formula)?
- Suppose you have a machine that executes each instruction sequentially (no overlap between instructions). The average CPI for this machine is 4. Multiplies account for 10% of all instructions. If you reduce the time for a multiply from 10 cycles to 3 cycles, what is the new CPI?
- With very accurate (>95%) branch prediction, adding an additional decode stage to a pipeline has little (<5%) effect on CPI (True or False).
- Adding buffering to an I/O system generally increases the need for bandwidth. (True or False)
- Convert -1023ten into a 16-bit two's complement binary number.
- What hexadecimal number does this binary number represent: 1100101011111110two ?
- Consider three machines with different cache configurations:
- Cache1: Directed-mapped with one-word blocks
- Cache2: Directed-mapped with four-word blocks
- Cache3: Two-way set associative with four-word blocks
- Cache2: Directed-mapped with four-word blocks
- The following missing rate measurements have been made:
- Cache 1: Instruction missing rate is 6%; data miss rate is 8%.
- Cache 2: Instruction missing rate is 4%; data miss rate is 5%.
- Cache 3: Instruction missing rate is 4%; data miss rate is 4%.
- Cache 2: Instruction missing rate is 4%; data miss rate is 5%.
- For these machines, one-half of the instructions contain a data reference. Assume that the cache miss penalty is 6 + Block size in words. The CPI for this workload was measured on a machine with Cache1 and was found to be 2.0.
- (10 points) Calculate the cycles on cache misses of each machine and determine which machine spends the most cycles .
- (4 points). The cycle times are 4ns for the first & second machine and 4.8ns for the third machine. Determine which machine is the fastest and which is the slowest.
| loop | lw | $u1,0($b0) | #Read next word from source | |
| addi | $u0,$u0,1 | #Increment count words copied | ||
| sw | $u1,0($b1) | #Write to destination | ||
| addi | $b0,$b0,1 | #Advance pointer to next source | ||
| addi | $b1,$b1,1 | #Advance pointer to next destination | ||
| bne | $u1,$zero,loop | # Loop if word copied is not equal to 0 |
| Instruction class | CPI | Frequency |
| A | 2 | 40% |
| B | 3 | 25% |
| C | 3 | 25% |
| D | 3 | 10% |
- What is the CPI (clock cycle per instruction ) of the processor?
- What is the MIPS (million instructions per second) for the processor
Later the compiler of the processor was improved to enhance the performance. The instruction improvements from this enhanced compiler have been estimated as follows:Instruction class Percentage of instructions executed vs. old compiler A 90% B 80% C 85% D 90%
- For the same program, what is the CPI for the processor with the enhanced compiler?
- How many times faster is achieved by using the enhanced compiler?
- (4 points) Draw its schematic using AND, OR, and inverter gates.
- (6 points) Using Boolean algebra, put the function into its minimized form and draw the resulting schematic.
Consider the following proposal for a new MIPS-architecture processor. The MIPS R9000 will have a 9-stage pipeline. The stages are as follows:
| F1 | Instruction Fetch 1: Instruction Address presented to I-Cache |
| F2 | Instruction Fetch 2: I-Cache produces instruction |
| R1 | Register Files are accessed. Instruction Decode Begins |
| R2 | Register file access completes, branch target computed, start computing branch condition. |
| A1 | ALU operations (including address for ld/st) start, Branch condition completed. |
| A2 | ALU operations are completed |
| M1 | Data Access 1: Data Address presented to D-Cache |
| M2 | Data Access 2: D-Cache produces data or completes store.. |
| W | Write results back to register file |
Although memory accesses take 2 cycles, they are fully pipelined so that one instruction fetch (I) and one data access (M) can begin every cycle. Similarly, the two-cycle register fetch and execution are also pipelined so that, in the absence of hazards, an instruction can be executed each cycle. All possible bypasses are present. There is no dynamic branch prediction.
Remember that there is 1 branch delay slot. Hardware interlocks are used to resolve pipeline hazards.
Assume that 8 NOPs precede and follow each code fragment - so only the instructions shown affect the pipeline. Remember that MIPS code lists the destination register first followed by source registers.
- (4 points)
Consider the following Code:add r1,r4,r5 add r7,r1,r5
For how many cycles will the second add stall? At which stage will the second add stall (that is, what is the last stage that is completed before the add must wait for the result of a previous instruction)? - (4 points)
Now consider the following code:lw r1,0(r5) add r7,r1,r5
For how many cycles will the add stall? At which stage will the add stall?
Given a circuit below. Suppose the output of gate G2 is stuck-at-zero due to a manufacturing defect (i.e. its logic level is always at low regardless the values at its inputs). Derive an input pattern to differentiate a bad circuit from a good one. In other words, assign values to x1, x2, x3, and x4 such that the output z1 will show different logic levels for a good circuit and a bad circuit, respectively. You must explain how you derive the answer.
