F(A, B, C, D) =
m(2,
5, 6, 8, 9, 10, 11, 12, 13, 14, 15)| Example: | X1: | 0 1 1 0 1 0 0 1 1 0 |
| X2: | 0 1 1 1 0 0 1 0 1 0 | |
| Z: | 0 1 1 1 1 0 0 1 1 1 |
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| （共1頁第1頁） |
| 1. | (a) | Simplify the following Boolean function
in (1) sum of products and (2) product of sums. F(A, B, C, D) = m(2,
5, 6, 8, 9, 10, 11, 12, 13, 14, 15) |
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| (b) | Implement the answers in (a) with (1) two-level NAND and (2) two-level NOR gates circuits | ||||||||||||
| (c) | Implement the above Boolean function in (a) with an 8�e1 Multiplexer and inverters. | ||||||||||||
| (d) | If we implement the above circuits with CMOS process, please compare the transistor counts and specify which way, two-level NAND, NOR or Multiplexer, meets the minimum number of MOS transistors? | ||||||||||||
| (Hint: 8x1 Multiplexer is implemented with CMOS transmission gates.) | |||||||||||||
| (40%) | |||||||||||||
| 2. | A Mealy sequential network has 2 inputs X1, X2 and 1 output Z. If the total number of 1’s received is �d 2 in the previous and present pairs of inputs, then the output should be “1” coincident with the present pair of inputs. | ||||||||||||
| (a) | Derive its state graph and state table. | ||||||||||||
| (b) | Using your answer in (a), implement this network with D Flip-Flops and Logic Gates. | ||||||||||||
| Please draw the circuit diagrams of this network. | (35%) | ||||||||||||
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| 3. | Analyze the following Flip-Flop circuit using a flow table. According to the flow table, please specify what kind of Flip-Flop is this circuit? And, it is positive-edge-triggered or negative-edge-triggered? | ||||||||||||
| Please write down your reasons. | (25%) | ||||||||||||
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