| 1. |
The graphical symbol of 16K*8 RAM chip is shown in the following figure,
where I is the input, O is the output, A is the address,
CS is the chip select, and RWS is the read/write select. (25%) |
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Design: |
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(a) 16K*32 RAM using 16K*8 RAM chips |
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(b) 64K*8 RAM using 16K*8 RAM chips |
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| 2. |
Reduce the following state table to a minimum number of states. (25%) |
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| 3. |
Based on the following state diagram for a specific counter, design
this counter by using clocked D flip-flops and other required basic gates. |
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(a) Derive the state table for above state diagram. (10%) |
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(b) Draw the logic diagram for this counter by using the clocked D flip-flops
and other required basic gates. (15%) |
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| 4. |
Analysis of clocked sequential networks (25%) |
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| (a) |
For the following unknown network, assume all Qs start from LOW
state, develop and draw the Q output waveforms (Q0, Q1, and Q2)
relative to the clock. (20%) |
| (b) |
What specific function does this device perform? (5%) |
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