| 1. | Suppose that for any program a conditional branch is always preceded by a compare instruction in architecture A. To optimize the performance of programs, architecture B that supports a compare-and-branch instruction is developed. The following facts are observed after comparing the two architectures:
| • | The clock rate of architecture A is 10% higher than that of architecture B. | |
| • | For architecture A, 20% of the instructions in a program are conditional branch instructions. |
| • | All instructions in architecture A take 2 clock cycles. |
| • | In architecture B, the compare-and-branch instruction takes 3 clock cycles, and all other instructions take 2 clock cycles. |
| (a) | (15 points) Which architecture is faster? Justify your answer quantitatively. |
| (b) | (10 points) To ensure that architecture B performs better, what is the maximum permissible decrease in the clock rate? |
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| 2. |
| (a) | (5 points) what is pipelined processor? |
| (b) | (20 points) Discuss pipeline hazards by giving classifications and conditions under which they might arise. |
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| 3. | Consider a fully associative cache which consists of 2 blocks. Suppose that there is a program which accesses memory blocks in the following order.
b a b d a c a b d c
| (a) | (9 points) What is the number of cache misses that will result if the cache uses the FIFO replacement policy? |
| (b) | (8 points) What is the number of cache misses that will result if the cache uses the LRU replacement policy? |
| (c) | (8 points) What is the number of cache misses that will result if the cache uses the most recently used(MRU) replacement policy? |
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| 4. | (25 points)Contrast the advantges and disadvantages of a single-bus versus a three-bus DLX architecture . Describe your answer in terms of cost , performance and ease of implementation.
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