私立中原大學八十八學年度博士班招生考試命題紙

所組別：

電子工程學系博士班甲組

科目：

數位系統

考試時間：

06月09日第 1節

1(60%)	A half-adder is a circuit for adding two binary bits. A full-adder is known as a circuit that accepts one bit of each operand an input carry and produces a sum bit an output carry.
	(1)(10%)	Please show the K-maps and equations for a half-adder.
	(2)(10%)	Please show the K-maps for a full-adder.
	(3)(10%)	please give the Boolean functions for the full-adder in terms of exclusive-OR operations.
	(4)(10%)	Please realize a full adder by interconnection of two half adders.
	(5)(20%)	We consider here a model of a half adder circuit in the VHDL language as shown below. Please design a full adder in VHDL, incorporating the half adder model.

	architecture STRUCTURE of HALF_ADDER is
	component AND2
	port(x,y:in bit ;o: out bit);
	component EXOR2
	port(x,y:in bit ;o: out bit);
	begin
	G1: AND2
	port map(a,b,carry);
	G2: EXOR2
	port map(a,b,sum);
	end STRUCTURE;

2(40%)	Design a sequential circuit having one input, X, and one output, Z. Z is to be 1 whenever the four most recent inputs are 0100, where the most recent input is the rightmost in the string. Overlapping of sequences is allowed so that the input seqence 0100100 will produce an output of 0001001. Both the inputX and tje output Z are to be asserted high. Let state A correspond to the situation where we have seen no part of the input sequence. Then let state B be the state corresponding to seeing the first 0 in the sequence. C can correspond to 01, and D to 010.
	(1)(10%)	Construct a state table for a Mealy machine
	(2)(10%)	Assume the assignment of the four states is made on two state variables (Y1,Y2) as follows (00)=A,(01)=B, (11)=C, and (10)=D. Form a transition table on this assignment.
	(3)(10%)	Derive the flip-flop excitation tables from the transition table if JK flip-flop are used.
	(4)(10%)	Derive the flip-flop input equations and the circuit output equation from the excitation tables.

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